1. Field of the Invention
The present invention relates to an evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing method.
2. Description of the Related Art
A chemical mechanical polishing method (CMP method) has been used for forming a semiconductor device. As normally, a plurality of semiconductor devices are simultaneously formed on a semiconductor wafer, and such CMP method is applied on the semiconductor wafer.
In the case where the CMP method is applied for a damascene process, an erosion in a densely packed region where many contact holes or conductive lines are thick in a narrow distance may occur. The erosion is whereby a thickness of an insulating region in the densely packed region becomes thin by the CMP method, compared with a predetermined thickness. The reason reported is that a speed of polishing the insulating layer becomes faster in the densely packed region.
If the thickness of the insulating layer becomes thinner beyond a permissible range by the erosion, it is possible that an insulation is broken or a current leak occurs in the semiconductor device.
The semiconductor wafer which includes such semiconductor device having such excessive erosion is evaluated as a defective product by measuring the thickness of the insulating layer. A contact type device for measuring bumps which have occurred by the erosion is used for such measurement.
As the contact type device directly contacts with elements in the semiconductor device, it is possible to damage the elements. As a result, such damage may decline a yield of the semiconductor device.